SIM-DSP: A DSP-Enhanced CAD Platform for Signal Integrity Macromodeling and Simulation

Macromodeling-Simulation process for signal integrity verifications has become necessary for the high speed circuit system design. This paper aims to introduce a “VLSI Signal Integrity Macromodeling and Simulation via Digital Signal Processing Techniques” framework (known as SIM-DSP framework), which applies digital signal processing techniques to facilitate the SI verification process in the pre-layout design phase. Core identification modules and peripheral (pre-/post-)processing modules have been developed and assembled to form a verification flow. In particular, a single-step discrete cosine transform truncation (DCTT) module has been developed for modeling-simulation process. In DCTT, the response modeling problem is classified as a signal compression problem, wherein the system response can be represented by a truncated set of non-pole based DCT bases, and error can be analyzed through Parseval’s theorem. Practical examples are given to show the applicability of our proposed framework

Exploiting implicit information from data for linear macromodeling

In macromodeling, data points of sampled structure responses are always matched to construct linear macromodels for transient simulations of packaging structures. However, implicit information from sampled data has not been exploited comprehensively to facilitate the identification process. In this paper, we exploit implicit information from the sampled data for linear marcomodeling. First, in order to include complementary data for a more informative identification, we propose a discrete-time domain identification framework for frequency-/time-/hybrid-domain macromodeling. Second, we introduce pre-/post-processing techniques (e.g., P-norm identification criterion and warped frequency-/hybrid-domain identification) to interpret implicit information for configurations of identifications. Various examples from chip-level to board-level are used to demonstrate the performance of the proposed framework. © 2013 IEEE.published_or_final_versio

CPU-GPU hybrid parallel binomial American option pricing

We present in this paper a novel parallel binomial algorithm that computes the price of an American option. The algorithm partitions a binomial tree constructed for the pricing into blocks of multiple levels of nodes, and assigns each such block to multiple processors. Each of the processors then computes the option's values at its assigned nodes in two phases. The algorithm is implemented and tested on a heterogeneous system consisting of an Intel multi-core processor and a NVIDIA GPU. The whole task is split and divided over and the CPU and GPU so that the computations are performed on the two processors simultaneously. In the hybrid processing, the GPU is always assigned the last part of a block, and makes use of a couple of buffers in the on-chip shared memory to reduce the number of accesses to the off-chip device memory. The performance of the hybrid processing is compared with an optimised CPU serial code, a CPU parallel implementation and a GPU standalone program.published_or_final_versio

Using web 2.0 tools to enhance learning in higher education: A case study in technological education

Pedagogy with Web 2.0 technologies is shown to facilitate the teaching-learning process through content sharing and idea collaboration. In this paper, we explore the possibility of using social networking tools, to support teaching practice in technological courses. In our study, we utilized i) Facebook Page as a platform to share content, experiences and news of a general engineering course, and ii) blog as a collaborative writing tool to express thoughts and opinions in a common core (general education) course. After our one-semester (three- months) study, we found that Facebook Page is an easy-to- use and familiar tool for students to share and exchange ideas among classmates, peers and public.published_or_final_versio

Binomial American Option Pricing on CPU-GPU Hetergenous System

Abstract-We present a novel parallel binomial algorithm to compute prices of American options. The algorithm partitions a binomial tree into blocks of multiple levels of nodes, and assigns each such block to multiple processors. Each processor in parallel with the others computes the option's values at nodes assigned to it. The computation consists of two phases, where the second phase can not start until the valuation in the first phase has been completed. The algorithm is implemented and tested on a heterogeneous system consisting of an Intel multicore processor and a NVIDIA GPU. The whole task is split and divided over the CPU and GPU so that the computations are performed on the two processors simultaneously. In the hybrid processing, the GPU is always assigned the last part of a block, and makes use of a couple of buffers in the on-chip shared memory to reduce the number of accesses to the off-chip device memory. The performance of the hybrid processing is compared with an optimised CPU serial code, a CPU parallel implementation and a GPU standalone program. We learned from the experiments that the lack of explicit mechanism in CUDA for synchronising CPU and GPU executions is a major obstacle for the hybrid processing to achieve high performance

A concurrent error detection based fault-tolerant 32 nm XOR-XNOR circuit implementation

As modern processors and semiconductor circuits move into 32 nm technologies and below, designers face the major problem of process variations. This problem makes designing VLSI circuits harder and harder, affects the circuit performance and introduces faults that can cause critical failures. Therefore, fault-tolerant design is required to obtain the necessary level of reliability and availability especially for safety-critical systems. Since XOR-XNOR circuits are basic building blocks in various digital and mixed systems, especially in arithmetic circuits, these gates should be designed such that they indicate any malfunction during normal operation. In fact, this property of verifying the results delivered by a circuit during its normal operation is called Concurrent Error Detection (CED). In this paper, we propose a CED based fault- tolerant XOR-XNOR circuit implementation. The proposed design is performed using the 32 nm process technology.published_or_final_versio

PAFSV: A Formal Framework for Specification and Analysis of SystemVerilog

We develop a process algebraic framework PAFSV for the formal specification and analysis of IEEE 1800TM SystemVerilog designs. The formal semantics of PAFSV is defined by means of deduction rules that associate a time transition system with a PAFSV process. A set of properties of PAFSV is presented for a notion of bisimilarity. PAFSV may be regarded as the formal language of a significant subset of IEEE 1800TM SystemVerilog. To show that PAFSV is useful for the formal specification and analysis of IEEE 1800TM SystemVerilog designs, we illustrate the use of PAFSV with a multiplexer, a synchronous reset D flip-flop and an arbiter

Design and realization of a smart battery management system

Battery management system (BMS) emerges a decisive system component in battery-powered applications, such as (hybrid) electric vehicles and portable devices. However, due to the inaccurate parameter estimation of aged battery cells and multi-cell batteries, current BMSs cannot control batteries optimally, and therefore affect the usability of products. In this paper, we proposed a smart management system for multi-cell batteries, and discussed the development of our research study in three directions: i) improving the effectiveness of battery monitoring and current sensing, ii) modeling the battery aging process, and iii) designing a self-healing circuit system to compensate performance variations due to aging and other variations.published_or_final_versio

Finishing the euchromatic sequence of the human genome

The sequence of the human genome encodes the genetic instructions for human physiology, as well as rich information about human evolution. In 2001, the International Human Genome Sequencing Consortium reported a draft sequence of the euchromatic portion of the human genome. Since then, the international collaboration has worked to convert this draft into a genome sequence with high accuracy and nearly complete coverage. Here, we report the result of this finishing process. The current genome sequence (Build 35) contains 2.85 billion nucleotides interrupted by only 341 gaps. It covers ∼99% of the euchromatic genome and is accurate to an error rate of ∼1 event per 100,000 bases. Many of the remaining euchromatic gaps are associated with segmental duplications and will require focused work with new methods. The near-complete sequence, the first for a vertebrate, greatly improves the precision of biological analyses of the human genome including studies of gene number, birth and death. Notably, the human enome seems to encode only 20,000-25,000 protein-coding genes. The genome sequence reported here should serve as a firm foundation for biomedical research in the decades ahead